In the world of computer brain-building, processors are like super-smart puzzle solvers. To make them even better, we use something called Finite State Machines (FSMs). In this blog post, we’re going to talk about why we add FSMs to the processor’s brain (RTL) and how we can do it in simple steps.

```
Reset Detector
always@(posedge clk)
begin
if(sys_rst)
state <= idle;
else
state <= next_state;
end
```

```
idle: begin
IR = 32'h0;
PC = 0;
next_state = fetch_inst;
end
fetch_inst: begin
IR = inst_mem[PC];
next_state = dec_exec_inst;
end
```

```
dec_exec_inst: begin
decode_inst();
decode_condflag();
next_state = delay_next_inst;
end
With this we have decoded the instruction, we will be giving a delay for next instruction to be loaded
which we will discuss soon!
```

```
next_inst: begin
next_state = sense_halt;
if(jmp_flag == 1'b1)
PC = `isrc;
else
PC = PC + 1;
end
```

```
sense_halt: begin
if(stop == 1'b0)
next_state = fetch_inst;
else if(sys_rst == 1'b1)
next_state = idle;
else//////////////////next state decoder + output decoder
always@(*) * because it is a combinational block
begin
case(state)
idle: begin
IR = 32'h0;
PC = 0;
next_state = fetch_inst;
end
fetch_inst: begin
IR = inst_mem[PC];
next_state = dec_exec_inst;
end
dec_exec_inst: begin
decode_inst();
decode_condflag();
next_state = delay_next_inst;
end
delay_next_inst:begin
end
next_inst: begin
next_state = sense_halt;
if(jmp_flag == 1'b1)
PC = `isrc;
else
PC = PC + 1;
end
sense_halt: begin
if(stop == 1'b0)
next_state = fetch_inst;
else if(sys_rst == 1'b1)
next_state = idle;
else
next_state = sense_halt;
end
default : next_state = idle;
endcase
end
next_state = sense_halt;
end
```

Integrating delay in above combinational circuit will not work..

Because it is sequential so we will create a new always clock block with positive edge of clock

Now we know that next instruction will be fetched after count of 4

```
delay_next_inst:begin
if(count < 4)
next_state = delay_next_inst;
else
next_state = next_inst;
end
```

```
always@(posedge clk)
begin
case(state)
idle : begin
count <= 0;
end
fetch_inst: begin
count <= 0;
end
dec_exec_inst : begin
count <= 0;
end
delay_next_inst: begin
count <= count + 1;
end
next_inst : begin
count <= 0;
end
sense_halt : begin
count <= 0;
end
default : count <= 0;
endcase
```

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