when slave address is placed in DR register then ADDR bit set but when control return from the address phase function the bit is cleared automatically . PS: this happens only in debug mode

I’m using nucleo-f446re for sending data by uart when i use uart2 it’s not working but when i use uart1 then it works can anyone tell me why it’s happening. I using PA2->Usart2_tx PA3->Usart2_rx While usart1 PA9->Usart1_tx PA10->Usart1_rx