Day 5 of 100 Days of RTL Projects-UART Design-Part 1

Understanding UART: A Fundamental Serial Communication Protocol

UART, standing for Universal Asynchronous Receiver and Transmitter, is a cornerstone of serial communication protocols. Before delving into its intricacies, let’s grasp the essence of a serial communication protocol and its significance.

Imagine two systems eager to exchange data. Whether they are digital computers, processors, or peripherals, the need for effective communication arises. Parallel communication, while feasible, becomes impractical with increasing data width. Thus, serial communication, transmitting one bit at a time, emerges as a solution.

Within a serial communication setup, a transmitting system loads data in parallel, then sends it over a single wire to a receiver. Both systems synchronize their actions, shifting data bit by bit. This streamlined process facilitates efficient data transfer between systems.

UART, among various serial communication protocols like I²C, SPI, and Ethernet, remains relevant despite its age. Its simplicity, albeit slower compared to modern standards like USB, makes it a preferred choice for many peripherals and sensors.

Originating from the RS232 protocol of the 1960s, UART has stood the test of time. Even in contemporary designs, UART finds application through interfaces like Digilent’s Pmods. These modules extend functionality to FPGA-based systems, demonstrating UART’s enduring utility.

Understanding UART goes beyond mere acknowledgment of its existence. Delving into its workings unveils a realm of timing intricacies and data transmission nuances. Constructing a UART module involves components like FIFOs, baud rate generators, receivers, and transmitters, each playing a crucial role in the data exchange process.

In learning to construct a UART module using Verilog, one gains not only a deeper understanding of UART but also a foundational knowledge applicable across various serial communication protocols. As we navigate through the intricacies of UART construction, we pave the way for mastering more complex communication systems.

The Essence of UART

The UART, or Universal Asynchronous Receiver/Transmitter, serves as a fundamental serial communication protocol, transmitting data sequentially, one bit at a time, over a single wire. Despite its apparent simplicity, UART adheres to a specific protocol, essential for reliable communication. Let’s delve into how a transmitter sends a byte of data to a receiver, delineating each step of the process.

To commence, during idle periods, the wire connecting the transmitter and receiver maintains a high voltage state, typically represented as ‘1.’ This high state signifies readiness and ensures a stable baseline for communication. When the transmitter intends to initiate communication, it lowers the wire’s voltage, signaling the start of data transmission. This lowered voltage, termed the start bit, marks the beginning of the data stream. In the UART protocol, a ‘bit’ refers to the duration the line remains in a specific state, typically ‘0’ for the start bit.

Following the start bit, the transmitter proceeds to transmit the data bits sequentially, beginning with the least significant bit (LSB) and ending with the most significant bit (MSB). Each bit, denoted as d0 to d7 in our example, represents a binary digit of the transmitted byte. The order of transmission usually follows the convention of transmitting the LSB first and then progressing to higher-order bits.

Upon transmitting all data bits, regardless of the final bit’s value, the transmitter returns the wire to a high voltage state, signaling the end of data transmission. This elevated voltage, termed the stop bit(s), serves as a delimiter, indicating the conclusion of the data byte. The duration of the stop bit(s) is typically predetermined and agreed upon by the transmitter and receiver before communication commences. Commonly, stop bits may be one, one and a half, or two bits in length, with the specific duration determined during the configuration phase.

Critical to effective communication is the agreement between the transmitter and receiver regarding various parameters governing data transmission. These parameters include the number of bits per word, which may range from 6 to 8 bits, the number of stop bits, and whether to incorporate a parity bit for error detection and correction. Parity, whether odd or even, serves as an additional mechanism to ensure data integrity by detecting transmission errors.

It is important to note that UART communication operates without a shared clock signal between the transmitter and receiver. Instead, both parties rely on agreed-upon parameters, including the baud rate, to synchronize data transmission. The baud rate specifies the speed at which data is transmitted and received, typically expressed in bits per second (bps). Popular baud rates, such as 9600 bps, facilitate widespread compatibility and efficient communication.

Physically, the receiver employs an oversampling scheme to accurately detect and interpret incoming data. Oversampling involves continuously monitoring the wire and sampling its voltage level multiple times per bit duration. The receiver samples the wire at a rate significantly higher than the baud rate, typically 16 times faster, to accurately determine the middle point of each bit. By accurately aligning with the midpoint of each bit, the receiver can reliably detect and interpret incoming data.

As it turns out, the receiver continuously monitors the wire, perpetually sampling its voltage levels. This relentless monitoring is essential to determine the wire’s state accurately—whether it remains idle, transitions to a low voltage level, or experiences rapid changes indicative of data transmission. This process, known as sampling, occurs at a rate significantly higher than the baud rate, ensuring precise detection of changes in voltage levels.

To illustrate, let’s assume a baud rate of 9600 bits per second (bps). To adequately sample the wire, the receiver multiplies this baud rate by 16. This oversampling approach guarantees that the receiver captures every subtle change in voltage, crucial for accurate data reception.

Now, let’s explore how the receiver initiates and synchronizes its sampling process:

Initially, the receiver observes the wire, awaiting any indications of activity. If the wire remains in an idle state, no action is taken; however, once the wire transitions from idle to an active state (e.g., a low voltage level), the receiver springs into action.

Upon detecting the transition, the receiver initiates a timer—a vital component in synchronizing the sampling process. This timer, akin to a standard counter or timer, begins counting intervals to align with the midpoint of each data bit. Given the oversampling rate of 16 times the baud rate, the receiver aims to reach 16 ticks per bit duration.

Before proceeding with the full 16-tick count, an essential step occurs: the timer reaches the midpoint. This midpoint, approximately the seventh tick in a 16-tick cycle, marks the ideal moment to recalibrate the timer. By halting at this juncture, the receiver ensures alignment with the middle of each bit—a critical aspect of accurate data interpretation. This recalibration involves resetting the timer and initiating a new count, commencing from zero.

With the timer synchronized and aligned to the midpoint of a bit, the receiver proceeds to perform the full 16-tick count. Each tick represents a discrete time interval within the bit duration, facilitating precise sampling. As the timer progresses from zero to 15, the receiver captures the voltage levels corresponding to the transmitted data bit.

This process repeats for each data bit, with the receiver executing the 16-tick count for the entire duration of the data byte. If a parity bit is present, the receiver extends its sampling process to include this additional bit, ensuring comprehensive data analysis.

Finally, as the receiver nears the end of the data byte, it adjusts its sampling for the stop bit(s). By timing the stop bit(s) precisely—whether one, one and a half, or two bits—the receiver concludes its sampling process, signaling the end of data transmission.

In summary, oversampling plays a pivotal role in UART communication, enabling the receiver to accurately interpret data transmitted by the sender. By synchronizing its sampling process with the midpoint of each bit and extending its sampling duration to encompass all data bits, including any parity bits and stop bits, the receiver ensures robust and reliable data reception.