Day 4 of 100 Days of RTL Projects-Memory Swap using FSM

In this segment, we delve into the intricate world of finite state machines (FSMs) and their utilization as control units in systems processing data. Specifically, we embark on the design journey of a system employing an FSM to execute a memory swap operation between two registers within a register file.

Before delving into the technical intricacies, let’s take a moment to understand what a register file entails. Essentially, a register file is a collection of flip-flops, which can be organized using various technologies such as RAM, ROM, or physical registers. Each register file is characterized by its number of rows or lines, typically represented as 2^n, accommodating multiple bits of data in each line. It’s important to note that the implementation details of the register file, the ability to read and write data synchronously or asynchronously via independent ports.

Now, let’s introduce the concept of augmenting a register file with a swap functionality. Imagine we have two memory locations, each storing a value. Our objective is to interchange these values efficiently. This is where the FSM comes into play. We’ll orchestrate a series of steps to facilitate this swap operation seamlessly.

To comprehend the swap process, let’s break it down into three key steps:

1. Store: We begin by storing the value of one register temporarily.
2. Swap: Next, we copy the value from the second register to the first register’s location.
3. Retrieve: Finally, we copy the temporarily stored value to the second register’s location, completing the swap.

With these steps outlined, we proceed to design the circuitry incorporating the register file and the FSM. Multiplexers and logic gates are employed to facilitate data flow and control within the system.

To augment the register file with the memory swap functionality, we introduce additional circuitry and an FSM to control the swap operation. Here’s a detailed breakdown of the circuit components and their roles:

1. Finite State Machine (FSM):
   • The FSM serves as the control unit for the swap operation. It dictates the sequence of steps involved in the swap process and coordinates the actions of other circuit components.
   • The FSM transitions between four states: idle state (S0), read from register A (S1), read from register B (S2), and write to registers A and B (S3).
   • Transitions between states are triggered by the swap signal. When the swap signal is asserted, the FSM progresses through the states sequentially, ensuring the proper execution of the swap operation.
2. Input Signals:
   • Address A and Address B: These signals specify the memory addresses of the registers from which data will be read or written during the swap operation.
   • Data Input (Write Data): This signal carries the binary value to be written into the register file during the swap operation.
   • Swap Signal: When asserted, this signal triggers the FSM to initiate the memory swap process by transitioning through the swap states.
3. Multiplexers (MUX):
   • Multiplexers are used throughout the circuit to select between multiple input signals based on control signals from the FSM.
   • In the idle state, multiplexers simply pass through the address and data signals without modification.
   • During the swap operation, multiplexers route signals according to the current state of the FSM. For example:
     • In state S1, the multiplexer selects the address of register A for reading.
     • In state S2, the multiplexer selects the address of register B for reading.
     • In state S3, the multiplexer selects the address of register A for writing the data read from register B, and vice versa.

1. Register Addresses and Data Lines:
   • The register addresses (address A and address B) determine which registers are accessed during the swap operation.
   • The data lines carry the binary values stored in the registers during read and write operations.
2. Control Signals:
   • Write Enable Signal: Controls the writing of data into the selected register. It is synchronized with the clock signal to ensure reliable data storage.
   • Swap Signal: Acts as the trigger for initiating the swap operation. When asserted, it prompts the FSM to transition through the swap states.
3. Feedback Loop:
   • To ensure proper feedback during the swap operation, a feedback loop is established between the data read and data write lines.
   • Multiplexers are used to select between the external data input and the data read from the register file, allowing for seamless data transfer during the swap process.

The code

Make one simple register file

module reg_file
#(parameter ADDR_WIDTH = 7, DATA_WIDTH = 8)(
input clk,
input we,
input [ADDR_WIDTH – 1: 0] address_w, address_r,
input [DATA_WIDTH – 1: 0] data_w,
output [DATA_WIDTH – 1: 0] data_r
);

reg [DATA_WIDTH - 1: 0] memory [0: 2 ** ADDR_WIDTH - 1];

always @(posedge clk)
begin
    // Synchronous write port
    if (we)
        memory[address_w] <= data_w;                              
end

// Asynchronous read port
assign data_r = memory[address_r];

endmodule

Now code fsm for swap

module swap_fsm(
input clk, reset_n,
input swap,
output w,
output [1:0] sel
);

reg [1:0] state_reg, state_next;
parameter s0 = 0, s1 = 1, s2 = 2, s3 = 3;

// Sequential state register
always @(posedge clk, negedge reset_n)
begin
    if (~reset_n)
        state_reg <= s0;
    else
        state_reg <= state_next;
end

// Next state logic
always @(*)
begin
    state_next = state_reg;
    case(state_reg)
        s0: if (~swap)  state_next = s0;
            else        state_next = s1;
        s1: state_next = s2;
        s2: state_next = s3;
        s3: state_next = s0;
        default: state_next = s0;
    endcase
end

// output logic
assign sel = state_reg;
assign w = (state_reg != s0);

endmodule

• state_reg, state_next: 2-bit registers used to store the current and next states of the FSM, respectively.
• s0, s1, s2, s3: Parameters representing the states of the FSM.

1. State Register:

• The state_reg register stores the current state of the FSM. It is updated on every rising edge of the clock (posedge clk) and when the reset signal is asserted (negedge reset_n).

1. Next State Logic:

• The state_next signal represents the next state of the FSM based on the current state and input signals.
• The always @(*) block is sensitive to any change in input signals.
• Using a case statement, the module determines the next state based on the current state (state_reg) and the swap input signal.
• If swap is asserted, the FSM transitions from s0 to s1. Otherwise, it remains in state s0. The other transitions occur sequentially from s1 to s2, s2 to s3, and finally from s3 back to s0.

1. Output Logic:

• The sel output signal is directly assigned the value of state_reg, representing the current state of the FSM.
• The w output signal indicates whether the FSM is in a state where swapping occurs (s1, s2, or s3). It is asserted when the current state is not s0.

Testbench

module swap_reg_file_tb(

);

localparam ADDR_WIDTH = 7;
localparam DATA_WIDTH = 8;
reg clk, reset_n;
reg we;
reg [ADDR_WIDTH - 1: 0] address_w, address_r;
reg [DATA_WIDTH - 1: 0] data_w;
wire [DATA_WIDTH - 1: 0] data_r;    
reg [ADDR_WIDTH - 1: 0] address_A, address_B;
reg swap;
integer i;

// Instantiate unit under test
swap_reg_file #(.ADDR_WIDTH(ADDR_WIDTH), .DATA_WIDTH(DATA_WIDTH)) uut(
    .clk(clk),
    .reset_n(reset_n),
    .we(we),
    .address_w(address_w),
    .address_r(address_r),
    .data_w(data_w),
    .data_r(data_r),
    .address_A(address_A),
    .address_B(address_B),
    .swap(swap)
);

// Generate stimuli
This block generates a clock signal clk with a period of T time units.

// Generating a clk signal
localparam T = 10;
always
begin
    clk = 1'b0;
    #(T / 2);
    clk = 1'b1;
    #(T / 2);
end

initial
begin
    // issue a quick reset for 2 ns
    reset_n = 1'b0;
    #2  
    reset_n = 1'b1;
    swap = 1'b0;


    // fill locations 20 to 30 with some numbers
    for (i = 20; i < 30; i = i + 1)
    begin
        @(negedge clk);
        address_w = i;
        data_w = i;
        we = 1'b1;            
    end

    we = 1'b0;
This initial block initializes signals, performs a reset, fills memory locations 20 to 30 with data, swaps locations 22 and 28 three times, and finally stops the simulation after a certain duration.
    // Swap 2 locations several times
    @(negedge clk)
    address_A = 'd22;
    address_B = 'd28;
    swap = 1'b1;
    repeat(3) @(negedge clk);
    swap = 1'b0;

    #25 $stop;


end    

endmodule